Ph.D., in Electrical Engineering, Sorbonne University Paris VI, France
M.Tech., Microelectronics, Indian Institute of Technology, Bombay
B.Tech., Electronics Engineering, Cochin University of Science and Technology, India
Dr. Vinod Pangracious joined AUD in Fall 2014 as Assistant Professor of Electrical Engineering. Prior to joining AUD, he was a research and development engineer at the Cypress Semiconductor Technology in San Jose, CA/Bangalore India and in 2004 he joined Infineon Technologies Germany to work with the Research and Development team to develop stack capacitor memories. In 2007, he moved to Switzerland to join Innovative Silicon a start-up company specialized in Zero Capacitor Memory.
Professor Vinod's research has focused on development 3D-NanoCAD and design methodologies for nano-scale semiconductor integrated circuits and reconfigurable architecture. Current focus of research in 3D-NanoCAD is design-assisted platform development to allow chip designers to combine silicon and non-silicon based semiconductor devices to optimize 3D chip design and its performance. For device and circuits side we specifically look at design automation techniques for assessing, enabling and optimizing semiconductor devices technologies as well as design-aware process integration.
V. Pangracious, Z. Marrakchi, H. Mehrez, Design and Optimization of Horizontally Partitioned High Speed 3-D Tree-based FPGA IEEE Micro Journal, vol, issue 99, DOI:10.1109/MM.2014.57, 2014.
V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez, Architecture level optimization of 3-dimensional tree-based FPGA, Microelectronics Journal 45 (4), 355-366, 2014.
V Pangracious, Z Marrakchi, N Beltaief, H Mehrez, U Farooq, Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA, 9th international Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2014.
V Pangracious, H Mehrez, Z Marrakchi , Design and optimization of heterogeneous tree-based FPGA using 3D technology, Field-Programmable Technology (FPT), 2013 International Conference on, 334-337 Kyoto Japan 2013.
V Pangracious, H Mehrez, Z Marakchi, Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology IEEE International conference on 3D Systems Integration Conference (3DIC), pp. 1-8, 2013.